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ASIC non-recurring engineering is dominated by three items: the mask set, engineering effort and EDA tools plus IP licences. At advanced nodes the mask set alone runs into millions, which is what pushes low-volume designs toward FPGAs or structured ASICs.
ASIC NRE
NRE = mask set + (person-months x rate) + tools and IP
Each of 60-90 layers needs an electron-beam-written reticle, and advanced nodes add multiple patterning plus EUV masks that cost far more per layer.
When volume amortises the NRE. The crossover is typically tens of thousands of units at mature nodes and hundreds of thousands at leading edge.