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DSP slice count is the required multiply rate divided by what one slice delivers at the DSP clock. Because the DSP clock usually exceeds the sample rate, each slice can be time-shared across several taps — 400 MHz against 50 MSPS gives eight multiplies per slice per sample.
DSP slices
slices = ceil(multiplies per sample x sample rate / DSP clock)
Running the multiplier faster than the sample rate so one physical DSP evaluates several taps per sample. It trades latency and control complexity for resource count.
When operand widths exceed the native size (typically 18x25 bits). Wider multiplies are decomposed into several slices plus adders.