Work out memory latency cycles instantly with clear inputs, formula shown and shareable results.
DRAM CAS latency in nanoseconds is the cycle count times the memory clock period, and that has barely improved across generations — CL36 at 3200 MHz is 11.25 ns, much the same as CL9 at 800 MHz. Adding controller and interconnect overhead gives the latency the CPU actually sees.
Memory latency
CAS ns = CL / memory clock; total = CAS ns + controller overhead; CPU cycles = ns x CPU GHz
Because latency is set by the sense amplifier and array physics, not the interface. Each generation raises bandwidth by widening and speeding the bus, leaving array access time roughly constant.
The CPU clock has risen faster than memory latency has fallen, so the same nanoseconds cost more cycles — the memory wall.