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Transistor density is count divided by die area, usually quoted in millions of transistors per square millimetre. It is the honest comparison between processes, because marketing node names no longer correspond to any physical dimension — density figures do.
Density
density (MTr/mm2) = transistor count / die area / 1e6
Since about 28 nm the number has been a marketing label rather than a gate length or half-pitch. Density in MTr/mm2 is the only meaningful cross-vendor comparison.
Roughly 90-100 MTr/mm2 at 7 nm, 130-170 at 5 nm and over 200 at 3 nm class processes, though logic and SRAM scale differently.