Work out cache size and associativity instantly with clear inputs, formula shown and shareable results.
Cache address decomposition: offset bits from line size, index bits from set count, and the rest are tag. Raising associativity reduces sets, which moves bits from index to tag and grows the tag array — the hidden area cost of higher associativity.
Cache mapping
sets = size / (line size x ways); index bits = log2(sets); tag bits = address - index - offset
Fewer sets means longer tags, and every way must be compared in parallel, so both tag array size and comparator count grow.
8-way for L1 data, 16-way for L2 and up to 16-32 way for shared L3. Beyond that the miss-rate benefit is negligible.