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Classical Dennard scaling shrinks area with the square of the linear factor while voltage falls proportionally, cutting dynamic power. Since voltage scaling stalled around 1 V, real power reduction lags the ideal — modelled here with a 1.5 power exponent rather than the classical cube.
Scaling
area scales as s^2 where s = new node / old node; power scales more slowly than the ideal s^3
Threshold voltage could not keep falling without leakage exploding, so supply voltage stopped scaling around 1 V and power density began rising with each node.
Logic comes close; SRAM and analogue scale much worse, and interconnect pitch scales worst of all, so real die shrink is less than the ideal.