Work out chip volume break even instantly with clear inputs, formula shown and shareable results.
The ASIC-versus-FPGA break-even is the NRE difference divided by the unit cost difference. Below that volume the FPGA wins on total cost; above it the ASIC does, and the gap widens linearly — which is why high-volume consumer parts are always ASICs.
Break-even volume
V = (ASIC NRE - FPGA NRE) / (FPGA unit cost - ASIC unit cost)
Time to market, the ability to fix bugs in the field, power and performance differences, and the risk that an ASIC respin adds mask cost and months of delay.
Reconfigurability, shorter schedule, lower risk and the option to change standards or algorithms after shipping. Those can outweigh unit cost.