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Clock power is C V squared f with an activity factor of one, because the clock switches every cycle by definition. That makes the clock tree typically 20-40% of total dynamic power in a synchronous design, and it is why clock gating is the single most effective power optimisation available.
Clock power
P = C V^2 f, with alpha = 1 since the clock always toggles
Every other net has an activity factor well below one; the clock's is exactly one and it reaches every sequential element on the die.
Typically 20-40% of total dynamic power, since most registers are idle most cycles. It is standard practice in all modern synthesis flows.