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Minimum clock period is logic delay plus clock-to-Q plus setup time plus clock uncertainty. The sequential overhead is fixed by the technology, so as pipelines get deeper and logic delay shrinks, that overhead becomes a larger fraction — the practical limit on pipelining.
Maximum frequency
Tmin = t_logic + t_clk-to-Q + t_setup + uncertainty; fmax = 1 / Tmin
Because the per-stage overhead does not shrink. Once logic delay approaches the flip-flop overhead, adding stages costs latency and power for almost no frequency gain.
Roughly 8-12 FO4 delays per stage in high-performance designs. Below that, register overhead and clock power dominate.