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Gate Propagation Delay Calculator

Work out gate propagation delay instantly with clear inputs, formula shown and shareable results.

About Gate Propagation Delay Calculator

Gate delay is an intrinsic term plus a load term of 0.69 x Rdrive x Cload. FO4 — an inverter driving four copies of itself — is the standard technology speed metric, and a rule of thumb is that a process's FO4 delay in picoseconds is roughly 0.5 times the node in nanometres.

Formula

Gate delay

tpd = t_intrinsic + 0.69 x Rdrive x Cload; FO4 uses a load of four identical gates

Worked example

With the default values below, Gate Propagation Delay Calculator returns Propagation delay of 20.28. Change any input above and every figure here is recalculated in your browser.

Inputs used

Fanout
4 loads
Input capacitance per load
2.5 fF
Effective drive resistance
1,200 Ω
Intrinsic delay
12 ps

Results

Propagation delay
20.28 ps
Total load capacitance
10.00 fF
Load-dependent delay
8.28 ps
FO4 reference delay
20.28 ps

Step by step

  1. 1Values used
  2. 2Gate delay
  3. 3Propagation delay= 20.28 ps
  4. 4Total load capacitance= 10.00 fF
  5. 5Load-dependent delay= 8.28 ps
  6. 6FO4 reference delay= 20.28 ps

Assumptions and limits

  • The result is derived only from the 4 inputs listed above. Anything not among them is not part of the calculation.
  • In particular, this calculator does not take inflation, tax or compounding frequency into account.
  • Figures are rounded for display to 2 decimal places, so totals built from several rounded parts can differ slightly from the unrounded arithmetic.

How these calculators are built and tested is described on the Methodology page. If a figure looks wrong, please report it.

Frequently Asked Questions

Why is FO4 the standard metric?

It is self-scaling and technology independent: the load is defined relative to the gate itself, so FO4 delays compare processes fairly.

How do I speed up a slow gate?

Reduce fanout, upsize the driver (lower Rdrive), or insert a buffer. Upsizing helps only until the larger gate's own input capacitance loads the previous stage.

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