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I2C Bus Capacitance Limit Calculator

Work out i2c bus capacitance limit instantly with clear inputs, formula shown and shareable results.

About I2C Bus Capacitance Limit Calculator

I2C is limited to 400 pF of bus capacitance because rise time is 0.8473 x R x C for the RC pull-up. Fast mode allows 300 ns of rise time, so the pull-up resistor and total capacitance together decide the maximum usable speed.

Formula

I2C rise time

tr = 0.8473 x Rpullup x Cbus; the specification limits Cbus to 400 pF

Worked example

With the default values below, I2C Bus Capacitance Limit Calculator returns Total bus capacitance of 260.00. Change any input above and every figure here is recalculated in your browser.

Inputs used

Devices on the bus
6 devices
Capacitance per device
10 pF
Total trace length
250 mm
Pull-up resistor
4,700 Ω

Results

Total bus capacitance
260.00 pF
Rise time
1,035.40 ns
Maximum bus speed
116 kHz
Assessment
Rise time too slow for fast mode

Step by step

  1. 1Values used
  2. 2I2C rise time
  3. 3Total bus capacitance= 260.00 pF
  4. 4Rise time= 1,035.40 ns
  5. 5Maximum bus speed= 116 kHz
  6. 6Assessment= Rise time too slow for fast mode

Assumptions and limits

  • The result is derived only from the 4 inputs listed above. Anything not among them is not part of the calculation.
  • In particular, this calculator does not take inflation, tax, fees or charges or compounding frequency into account.
  • Figures are rounded for display to 2 decimal places, so totals built from several rounded parts can differ slightly from the unrounded arithmetic.

How these calculators are built and tested is described on the Methodology page. If a figure looks wrong, please report it.

Frequently Asked Questions

Can I just use a smaller pull-up?

To a point. Lower resistance speeds the rise but raises the sink current, and the specification limits low-level output current to 3 mA, which sets a minimum resistance.

What if I exceed 400 pF?

Use an I2C buffer or bus extender, split the bus into segments, or switch to a multi-master-capable protocol designed for longer runs.

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